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a AD8560 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. rev. 0 12 out a 11 out b 10 out c 9 out d in a 1 in b 2 in c 3 in e 5 nc 6 nc 7 out e 8 in d 4 16 v+ 15 nc 14 nc 13 gnd pin 1 indicator top view AD8560 nc = no connect 16 v rail-to-rail buffer amplifier block diagram 56 in b in c in d out e out b out c out d out a 2 9 3 8 4 7 1 10 in e in a v+ gnd 16-lead lfcsp (cp suffix) features single-supply operation: 4.5 v to 16 v dual-supply capability from 2.25 v to 8 v input capability beyond the rails rail-to-rail output swing continuous output current: 35 ma peak output current: 250 ma offset voltage: 10 mv max slew rate: 8 v/ s stable with 1 f loads supply current applications lcd reference drivers portable electronics communications equipment general description the AD8560 is a low cost, five-channel, single-supply buffer amplifier with rail-to-rail input and output capability. the AD8560 is optimized for lcd monitor applications. these lcd buffers have high slew rates, a 35 ma continuous output drive, and high capacitive load drive capability. they have wide supply range and offset voltages below 10 mv. the AD8560 is specified over the ?0 c to +85 c temperature range. they are available on tape and reel in a 16 -lead lfcsp.
C2C rev. 0 AD8560?pecifications electrical characteristics parameter symbol conditions min typ max unit input characteristics offset voltage v os 210mv offset voltage drift ? v os / ? t ?0 c t a +85 c5 v/ c input bias current i b 80 600 na ?0 c t a +85 c 800 na input voltage range ?.5 v s + 0.5 v input impedance z in 400 k ? input capacitance c in 1pf output characteristics output voltage high v oh i l = 100 av s ?0.005 v v s = 16 v, i l = 5 ma 15.85 15.95 v ?0 c t a +85 c 15.75 v v s = 4.5 v, i l = 5 ma 4.2 4.38 v ?0 c t a +85 c 4.1 v output voltage low v ol i l = 100 a5mv v s = 16 v, i l = 5 ma 42 150 mv ?0 c t a +85 c 250 mv v s = 4.5 v, i l = 5 ma 95 300 mv ?0 c t a +85 c 400 mv continuous output current i out 35 ma peak output current i pk v s = 16 v 250 ma transfer characteristics gain a vcl r l = 2 k ? 0.995 0.9985 1.005 v/v ?0 c t a +85 c 0.995 0.9980 1.005 v/v gain linearity nl r l = 2 k ? , v o = 0.5 to (v s ?0.5 v) 0.01 % power supply supply voltage v s 4.5 16 v power supply rejection ratio psrr v s = 4 v to 17 v ?0 c t a +85 c7090 db supply current/amplifier i sy v o = v s /2, no load 780 1,000 a ?0 c t a +85 c 1,200 a dynamic performance slew rate sr r l = 10 k ? , c l = 200 pf 4.5 8 v/ s bandwidth bw ? db, r l = 10 k ? , c l = 10 pf 8 mhz phase margin o r l = 10 k ? , c l = 10 pf 65 degrees channel separation 75 db noise performance voltage noise density e n f = 1 khz 27 nv/ hz e n f = 10 khz 25 nv/ hz current noise density i n f = 10 khz 0.8 pa/ hz specifications subject to change without notice. (4.5 v v s 16 v, v cm = v s /2, t a = 25 c, unless otherwise noted.)
C3C AD8560 rev. 0 absolute maximum ratings * supply voltage (v s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v input voltage . . . . . . . . . . . . . . . . . . . . . . ?.5 v to v s + 0.5 v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . v s storage temperature range . . . . . . . . . . . . ?5 c to +150 c operating temperature range . . . . . . . . . . . ?0 c to +85 c junction temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature range (soldering, 60 sec) . . . . . . . . 300 c esd tolerance (hbm) . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 kv esd tolerance (cdm) . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kv * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package type ja 1 jc jb 2 unit 16-lead lfcsp (cp) 35 13 c/w notes 1 ja is specified for worst-case conditions, i.e., ja is specified for device soldered onto a circuit board for surface-mount packages. 2 jb is applied for calculating the junction temperature by reference to the board temperature. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD8560 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide temperature package package model range description option AD8560acp ?0 c to +85 c 16-lead lfcsp cp-16 available in reels only.
C4C AD8560 rev. 0 input offset voltage ?mv 100 0 12 9 qu antity ?amplifiers 6 3 0 36912 90 50 30 20 10 80 70 40 60 t a = 25 c 4.5v < v s < 16v tpc 1. input offset voltage distribution tcvos ? c 300 150 0 0 100 10 qu antity ?amplifiers 20 30 40 50 60 70 80 90 250 200 100 50 4.5v < v s < 16v tpc 2. input offset voltage drift distribution temperature ? c 0 0.25 1.50 40 input offset voltage ?mv +25 +85 0.50 0.75 1.00 1.25 v cm = v s /2 v s = 16v v s = 4.5v tpc 3. input offset voltage vs. temperature temperature ? c 0 50 350 40 input bias current ?na +25 +85 150 200 250 300 v cm = v s /2 v s = 16v v s = 4.5v 100 tpc 4. input bias current vs. temperature temperature ? c 5 5 40 input offset current ?na +25 +85 2 3 4 v s = 16v v s = 4.5v 1 4 3 2 1 0 tpc 5. input offset current vs. temperature temperature ? c 15.96 15.86 40 output voltage ?v +25 +85 15.89 15.88 15.87 v s = 16v v s = 4.5v 15.90 15.95 15.94 15.93 15.92 15.91 i load = 5ma 4.46 4.3 6 4.39 4.38 4.37 4.40 4.45 4.44 4.43 4.42 4.41 tpc 6. output voltage swing vs. temperature ?ypical performance characteristics
C5C AD8560 rev. 0 temperature ? c 150 0 40 output voltage ?mv +25 +85 45 30 15 v s = 16v v s = 4.5v 60 135 120 105 90 75 i load = 5ma tpc 7. output voltage swing vs. temperature temperature ? c 0.9999 0.9995 40 gain error ?v/v +25 +85 r l = 2k 4.5v < v s < 16v v out = 0.5v to 15v 0.9997 r l = 600 tpc 8. voltage gain vs. temperature load current ?ma 10 0.1 0.001 10 0 0.01 output voltage ? mv 0.1 1 10 1 100 1k t a = 25 c v s = 16v v s = 4.5v tpc 9. output voltage to supply rail vs. load current temperature ? c 0.85 0.55 40 supply current/amplifier ?ma +25 +85 0.70 0.65 0.60 v s = 16v v s = 4.5v 0.75 v cm = v s /2 0.80 tpc 10. supply current/amplifier vs. temperature temperature ? c 7 40 slew rate ?v/ s +25 +85 3 2 1 v s = 16v v s = 4.5v 4 r l = 10k c l = 200pf 5 6 8 tpc 11. slew rate vs. temperature supply voltage ?v 1.0 018 2 supply current/amplifier ?ma 46810 12 14 16 0.9 0.5 0.3 0.2 0.1 0.8 0.7 0.4 0.6 t a = 25 c a v = 1 v o = v s /2 1.1 tpc 12. supply current/amplifier vs. supply voltage
C6C AD8560 rev. 0 frequency ?hz 10 40 100k 100m gain ?db 10m 1m 35 30 25 20 15 10 5 5 0 1k 10k 560 150 t a = 25 c v s = 8v v in = 50mv rms c l = 40pf a v = 1 tpc 13. frequency response vs. resistive loading frequency ?hz 25 100k 100m gain ?db 10m 1m 25 20 15 10 5 20 0 1040pf 10 5 15 50pf 100pf 540pf t a = 25 c v s = 8v v in = 50mv rms r l = 10k a v = 1 tpc 14. frequency response vs. capacitive loading frequency ?hz 100 10m 1k impedance ? 10k 100k 1m 500 450 0 400 350 300 250 200 150 100 v s = 16v v s = 4.5v 50 tpc 15. closed-loop output impedance vs. frequency output swing ?vp-p fre q uency ?hz 10m 1m 100k 10k 1k 100 10 0 2 4 6 8 10 12 14 16 18 t a = 25 c v s = 16v a v = 1 r l = 10k distortion < 1% tpc 16. closed-loop output swing vs. frequency frequency ?hz 100 10m 1k power supply rejection ?db 10k 100k 1m 160 140 40 120 100 80 60 40 20 0 + psrr 20 psrr t a = 25 c v s = 16v tpc 17. power supply rejection ratio vs. frequency frequency ?hz 100 10m 1k power supply rejection ?db 10k 100k 1m 160 140 40 120 100 80 60 40 20 0 + psrr 20 psrr t a = 25 c v s = 4.5v tpc 18. power supply rejection ratio vs. frequency
C7C AD8560 rev. 0 frequency ?hz 1,000 100 1 10 10k 100 vo ltag e noise density ?nv/ hz 1k 10 t a = 25 c 4.5v v s 16v tpc 19. voltage noise density vs. frequency channel separation ?db frequency ?hz 100m 10m 1m 100k 10k 1k 100 180 140 120 100 80 60 40 20 0 20 t a = 25 c 4.5v < v s < 16v 160 tpc 20. channel separation vs. frequency load capacitance ? p f 100 90 0 10 1k 100 o vershoot ?% 80 70 60 50 40 30 20 10 t a = 25 c v s = 16v v cm = 8v v in = 100mv p-p a v = 1 r l = 10k os +os tpc 21. small signal overshoot vs. load capacitance load capacitance ?pf 100 90 0 10 1k 100 o vershoot ?% 80 70 60 50 40 30 20 10 t a = 25 c v s = 4.5v v cm = 2.25v v in = 100mv p-p a v = 1 r l = 10k os +os tpc 22. small signal overshoot vs. load capacitance settling time ? s 15 10 15 02.0 0.5 output swing from 0v to v 1.0 1.5 5 0 5 10 t a = 25 c v s = 8v r l = 10k o vershoot settling to 0.1% undershoot settling to 0.1% tpc 23. settling time vs. step size time ?2 s/div 0 0 00 0 vo lta ge ?2v/div 000000 0 0 0 0 0 0 0 t a = 25 c v s = 16v a v = 1 r l = 10k c l = 300pf tpc 24. large signal transient response
C8C AD8560 rev. 0 time ?2 c v s = 4.5v a v = 1 r l = 10k c l = 300pf tpc 25. large signal transient response time ?1 s/div 0 0 00 0 vo lta ge ?50mv/div 000000 0 0 0 0 0 0 0 t a = 25 c v s = 16v a v = 1 r l = 10k c l = 100pf tpc 26. small signal transient response time ?1 c v s = 4.5v a v = 1 r l = 10k c l = 100pf tpc 27. small signal transient response time ?40 s/div 0 0 00 0 vo lta ge ?3v/div 000000 0 0 0 0 0 0 0 t a = 25 c v s = 16v a v = 1 r l = 10k tpc 28. no phase reversal
C9C AD8560 rev. 0 applications theory of operation these buffers are designed to drive large capacitive loads in lcd applications. each has a high output current drive and rail-to- rail input/output operation and can be powered from a single 16 v supply. they are also intended for other applications where low distortion and high output current drive are needed. input overvoltage protection as with any semiconductor device, whenever the input exceeds either supply voltage, attention needs to be paid to the input overvoltage characteristics. as an overvoltage occurs, the amplifier could be damaged depending on the voltage level and the magnitude of the fault current. when the input voltage exceeds either supply by more than 0.6 v, internal pin junctions will allow current to flow from the input to the supplies. this input current is not inherently damaging to the device as long as it is limited to 5 ma or less. if a condition exists using the buffers where the input exceeds the supply by more than 0.6 v, a series external resistor should be added. the size of the resistor can be calculated by using the maximum overvoltage divided by 5 ma. this resistance should be placed in series with the input exposed to an overvoltage. output phase reversal the buffer family is immune to phase reversal. although the device? output will not change phase, large currents due to input overvoltage could damage the device. in applications where the possibility exists of an input voltage exceeding the supply voltage, overvoltage protec- tion should be used as described in the previous section. total harmonic distortion (thd+n) the buffer family features low total harmonic distortion. the total harmonic distortion plus noise for the buffer over the entire supply range is below 0.08%. when the device is powered from a 16 v supply, the thd + n stays below 0.03%. figure 1 shows the AD8560? thd + n versus the frequency performance. fre q uency ?hz 20 30k thd + n ?% 100 1k 10k 10 1 0.01 0.1 v s = 2.5v v s = 8v figure 1. thd + n vs. frequency short circuit output conditions the buffer family does not have internal short circuit protection circuitry. as a precautionary measure, do not short the output directly to the positive power supply or to the ground. it is not recommended to operate the AD8560 with more than 35 ma of continuous output current. the output current can be limited by placing a series resistor at the output of the amplifier whose value can be derived using the following equation: r v ma x s 35 for a 5 v single-supply operation, r x should have a minimum value of 143 ? . recommended land pattern for the AD8560 figure 2 is a recommended land pattern for the AD8560 pcb design. the recommended thermal pad size for the pcb design matches the dimensions of the exposed pad on the bottom of the package. the solder mask design for improved thermal pad contact to the exposed pad and reliability uses a stencil pattern for approximately 85% solder coverage. a minimum clearance of 0.25 mm is maintained on the pcb between the outer edges of the thermal pad and the inner edges of the pattern for the land to avoid shorting. for better thermal performance, thermal vias should also be used. since the AD8560 is relatively a low power part, just soldering the exposed package pad to the pcb thermal pad should provide sufficient electrical performance. 0.65 solder mask board metallization 1.95 2.1 0.25 0.875 0.20 0.05 0.1 0.4 0.9 0.28 0.75 typ 16 pl symm c l symm c l figure 2. 16-lead 4 x 4 land pattern
?0 AD8560 rev. 0 outline dimensions 16-lead lead frame chip scale package [lfcsp] 4 mm 4 mm body (cp-16) dimensions shown in millimeters 16 5 13 8 9 12 1 4 bottom view 2.25 2.10 1.95 0.75 0.60 0.50 0.65 bsc 1.95 bsc 0.35 0.28 0.25 12 max 0.20 ref seating plane pin 1 indicator top view 4.0 bsc sq 3.75 bsc sq 0.60 max 0.60 max 0.05 max 0.02 nom 0.80 max 0.65 nom compliant to jedec standards mo-220-vggc pin 1 indicator 1.00 0.90 0.80 coplanarity 0.08 sq
C11C
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